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| MTD20N06HD Preferred Device Power MOSFET 20 Amps, 60 Volts N-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient (Note 1) - Junction to Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID Value 60 60 20 30 20 16 60 40 0.32 1.75 -55 to 150 60 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 1 2 12 3 4 http://onsemi.com V(BR)DSS 60 V RDS(on) TYP 35 mW@10 V ID MAX 20 A (Note 1) N-Channel D G S MARKING DIAGRAMS 4 Drain DPAK CASE 369C Style 2 4 IDM PD 2 1 3 Drain Gate Source 4 Drain YWW 20N 06HD 123 Gate Drain Source Package DPAK DPAK Straight Lead DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel Publication Order Number: MTD20N06HD/D TJ, Tstg EAS 3 DPAK CASE 369D Style 2 20N06HD Device Code Y = Year WW = Work Week RJC RJA RJA TL 3.13 100 71.4 260 C/W ORDERING INFORMATION C Device MTD20N06HD MTD20N06HD-1 MTD20N06HDT4 1. When surface mounted to an FR-4 board using the minimum recommended pad size. 2. When surface mounted to an FR-4 board using the 0.5 sq.in. drain pad size. Preferred devices are recommended choices for future use and best overall value. (c) Semiconductor Components Industries, LLC, 2006 August, 2006 - Rev. 5 1 YWW 20N 06HD MTD20N06HD ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 7) (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc, RG = 9.1 ) td(on) tr td(off) tf QT (VDS = 48 Vdc, ID = 20 Adc, VGS = 10 Vdc) Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Cpk 8.0) (Note 3) Reverse Recovery Time (See Figure 14) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD Vdc - - - - - - 0.95 0.88 35.7 24 11.7 0.055 1.0 - - - - - C nH - - 4.5 7.5 - nH - ns - - - - - - - - 9.2 61.2 19 36 17 3.4 7.75 7.46 18 122 38 72 24 - - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 607 218 55 840 290 110 pF (Cpk 2.0) (Note 3) VGS(th) Vdc 2.0 - - - - 5.0 - 7.0 0.035 - - 6.0 4.0 - 0.045 Vdc 1.2 1.1 mhos - mV/C Ohm (Cpk 2.0) (Note 3) V(BR)DSS Vdc 60 - - - - - 54 - - - - - 10 100 100 mV/C Adc Symbol Min Typ Max Unit IDSS IGSS nAdc (Cpk 2.0) (Note 3) RDS(on) VDS(on) gFS trr (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) ta tb QRR LD LS Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk = Absolute Value of Spec (Spec-AVG/3.516 A). http://onsemi.com 2 MTD20N06HD TYPICAL ELECTRICAL CHARACTERISTICS 40 VGS = 10 V I D , DRAIN CURRENT (AMPS) 32 TJ = 25C 24 6V 16 40 7V I D , DRAIN CURRENT (AMPS) 30 VDS 10 V 9V 8V 20 10 100C 0 25C TJ = - 55C 2 3 4 5 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (Volts) 8 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5V 4.0 4.5 5.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Volts) Figure 1. On-Region Characteristics RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.052 0.048 0.044 0.040 0.036 0.032 0.028 - 55C 0.024 0.020 0 10 20 ID, DRAIN CURRENT (Amps) 30 40 25C VGS = 10 V TJ = 100C 0.040 Figure 2. Transfer Characteristics TJ = 25C 0.038 0.036 0.034 0.032 0.030 0.028 0 10 20 ID, DRAIN CURRENT (Amps) 30 40 15 V VGS = 10 V Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.6 VGS = 10 V ID = 10 A 1.4 1.2 1.0 0.8 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance Variation with Temperature http://onsemi.com 3 MTD20N06HD POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1600 VDS = 0 V 1400 Ciss C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 10 Coss Crss 15 20 25 Crss Ciss VGS = 0 V TJ = 25C The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts) Figure 6. Capacitance Variation http://onsemi.com 4 MTD20N06HD VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 VGS 8 6 4 2 0 ID = 20 A TJ = 25C 40 Q1 Q2 30 20 10 Q3 VDS 0 2 4 6 8 10 12 14 16 QG, TOTAL GATE CHARGE (nC) 0 18 50 60 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 VDD = 30 V ID = 20 A VGS = 10 V TJ = 25C 100 t, TIME (ns) tf td(off) 10 td(on) tr 1 1 10 RG, GATE RESISTANCE (Ohms) 100 Figure 7. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 8. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 20 18 I S , SOURCE CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 0.50 0.58 0.66 0.74 0.82 0.90 0.98 VGS = 0 V TJ = 25C high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. VSD, SOURCE-TO-DRAIN VOLTAGE (Volts) Figure 9. Diode Forward Voltage versus Current http://onsemi.com 5 MTD20N06HD di/dt = 300 A/s Standard Cell Density trr High Cell Density trr tb ta I S , SOURCE CURRENT t, TIME Figure 10. Reverse Recovery Time (trr) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 100 VGS = 20 V SINGLE PULSE TC = 25C 10 100 s 1 ms 10 ms dc 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1.0 10 100 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 s 60 ID = 20 A 50 40 30 20 10 0 I D , DRAIN CURRENT (AMPS) 25 50 75 100 125 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 6 MTD20N06HD TYPICAL ELECTRICAL CHARACTERISTICS r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 t1 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E-04 1.0E-01 1.0E+00 1.0E+01 Figure 13. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 7 MTD20N06HD INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection 6.20 0.244 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = TJ(max) - TA RJA PD = 150C - 25C = 1.75 Watts 71.4C/W The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 The 71.4C/W for the DPAK package assumes the use of 0.5 sq.in. source pad on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. Board Material = 0.0625 G-10/FR-4, 2 oz Copper 1.75 Watts 80 TA = 25C 60 3.0 Watts 40 5.0 Watts 20 0 2 4 6 A, AREA (SQUARE INCHES) 8 10 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. http://onsemi.com 8 MTD20N06HD SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 9 CCC CC C CCC CC C CC CCCCC C CC CCCCC C CCC CC CC CC CC CC SOLDER PASTE OPENINGS STENCIL MTD20N06HD TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" STEP 4 HEATING ZONES 3 & 6 "SOAK" DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 10 MTD20N06HD PACKAGE DIMENSIONS DPAK CASE 369C-01 ISSUE O -T- B V R 4 SEATING PLANE INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 --- C E DIM A B C D E F G H J K L R S U V Z S A 1 2 3 Z U K F L D G 2 PL J H 0.13 (0.005) T M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN DPAK CASE 369D-01 ISSUE O B V R 4 C E Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 --- S -T- SEATING PLANE A 1 2 3 K F D G 3 PL J H M 0.13 (0.005) T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN Thermal Clad is a registered trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 11 MTD20N06HD/D |
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